1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a driving apparatus thereof that are adaptive for eliminating a flicker caused by a pre-stage gate voltage as well as reducing power consumption.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of a liquid crystal cell in accordance with a video signal, thereby displaying image data (picture). For dynamically displaying image data (moving pictures), an active matrix LCD is provided with a switching device for each liquid crystal cell. The active matrix LCD generally uses a thin film transistor (TFT) as the switching device.
FIG. 1 is a block diagram showing a configuration of a conventional liquid crystal display. In FIG. 1, a driving apparatus for an LCD includes a digital video card 1 for converting an analog image signal into a digital video data, a data driver 3 for applying the digital video data to data lines DL of a liquid crystal display panel 6, a gate driver 5 for sequentially driving gate lines GL of the liquid crystal panel 6, and a controller 2 for controlling the data driver 3 and the gate driver 5.
In the liquid crystal panel 6, a liquid crystal material is injected between two glass substrates, and the gate and data lines GL and DL are orthogonally formed on the lower glass substrate. A thin film transistor (TFT) is formed at each intersection between the gate and data lines GL and DL for selectively applying an image inputted from the data lines DL to a liquid crystal cell Clc. The TFT has a drain terminal connected to the gate line GL and a source terminal connected to the data line DL. The drain terminal of the TFT is connected to a pixel electrode of the liquid crystal cell Clc.
The digital video card 1 converts an analog input image signal into a digital image signal suitable for the liquid crystal panel 6 and detects a synchronous signal included in the image signal. The controller 2 applies red (R), green (G) and blue (B) digital video data from the digital video card 1 to the data driver 3. In addition, the controller 2 generates a dot clock signal Dclk and a gate start pulse Gsp using horizontal/vertical synchronizing signals H and V inputted from the digital video card 1, thereby providing a timing control of the data driver 3 and the gate driver 5. The dot clock signal Dclk is applied to the data driver 3, while the gate start pulse Gsp is applied to the gate driver 5. The vertical synchronizing signal V has a frequency of 60 Hz and is created by a vertical synchronizing signal oscillator (not shown) provided at the digital video card 1. The vertical synchronizing signal V indicates a frame end of each field. On the other hand, the horizontal synchronizing signal H indicates an end of each line within a field and is created by a horizontal synchronizing signal (not shown) as given by the following equation:
 H=VR*RRv*1.05.  (1)
where H is the horizontal synchronizing signal, VR is the vertical resolution, and RRv is the refresh rate of the vertical synchronizing signal V.
FIG. 2 is a detailed block diagram of the gate driver shown in FIG. 1. In FIG. 2, the gate driver 5 includes a shift register 12 for responding to the gate start pulse Gsp inputted from the controller 2 to sequentially generate a scanning pulse, and a level shifter 14 for shifting a voltage of the scanning pulse into a voltage level suitable for a driving of the liquid crystal cell Clc. Video data at the data line DL is applied to a pixel electrode of the liquid crystal cell Clc by the TFT in response to the scanning pulse inputted from the gate driver 5.
The dot clock signal Dclk, along with the R, G and B digital video data from the controller 2, is inputted to the data driver 3. The data driver 3 latches the R, G and B digital video data in synchronization with the dot clock signal Dclk and corrects the latched data in accordance with a gamma voltage Vγ. Then, the data driver 3 converts data corrected by the gamma voltage Vγ into analog data and supplies the analog data to each data line DL.
FIG. 3 is an equivalent circuit diagram of a pixel having a storage-on-gate (SOG) structure shown in FIG. 1. In FIG. 3, the liquid crystal display panel 6 (in FIG. 1) includes a pixel electrode 16, and a TFT T1 arranged at each intersection between the gate and data lines GL and DL to function as a switching device. The pixel electrode 16 is an area for transmitting and extinguishing light that applies a signal voltage to a liquid crystal layer (not shown) to display a picture.
The TFT T1 functions as a switch to load and break a signal voltage to and from a pixel electrode 14 (in FIG. 1). A gate terminal of the TFT T1 is connected to the gate line GL and a drain terminal of the TFT T1 is connected to the pixel electrode 14 (in FIG. 1). Accordingly, the TFT T1 applied a pixel voltage to the pixel electrode 16 to display a picture. An auxiliary capacitor, i.e., a storage capacitor Cst, is used to improve a sustaining characteristic of a liquid crystal application voltage, stabilize a gray scale display, and maintain pixel information during a non-selection interval of a pixel.
The shift register (not shown) of the data driver 3 sequentially receives video signals for each data line DL to store video signals. Subsequently, the gate driver 5 outputs a gate line selection signal GL to sequentially select one gate line of a plurality of the gate lines GL. A plurality of TFT's T1 connected to the selected gate line GL are turned on to apply video signals stored in the shift register of the data driver 8 to the source terminals of the TFT's T1, thereby displaying the video signals on the liquid crystal display panel 6. Thereafter, this operation is repeated to display the video signals on the liquid crystal display panel. The storage capacitor Cst charges data voltage from a pre-stage gate line GLn−1 upon scanning of the gate line GLn.
FIGS. 4 and 5 are waveform diagrams illustrating a time-based change with respect to data voltage charged in the storage capacitor Cst. In FIG. 4, the storage capacitor Cst charges a positive(+) voltage during a 1H interval at which a scanning pulse has an ON state. The voltage charged in the storage capacitor Cst is sustained during one frame after a scanning pulse is turned OFF. In FIG. 5, the storage capacitor Cst charges a negative(−) voltage during a 1H interval at which a scanning pulse has an ON state. The voltage charged in the storage capacitor Cst is sustained during one frame after a scanning pulse is turned ON.
However, a conventional driving method for an LCD employing the storage capacitor Cst is problematic in that a deriving voltage allowing a high voltage of the pre-stage gate line GLn−1 to be derived into the storage capacitor Cst upon data charging of the storage capacitor Cst into the gate line GLn is added to a pixel voltage. Such a deriving voltage will be described in detail through simulation values of FIGS. 6 and 7. In FIGS. 6 and 7, when a gate voltage is 20V, the deriving voltage ΔV having a very high value of about 10V is applied to the pixel. Input signal values of FIGS. 6 and 7 are given by the following table:
TABLE 1Gate Pulse Width14.3μsGate High Voltage(Vgh)21.4VGate Low Voltage(Vgl)−5V1 Horizontal Sync. Interval15.2μsData High Voltage(Vdh)5.24VData Low Voltage(Vdl)1.56VCommon Voltage Data Low Voltage2.79V
Accordingly, since a voltage Vpixel applied to the pixel has a value in which the deriving voltage ΔV is added to the charged voltage, display data is distorted. The deriving voltage ΔV applied to the pixel has a value three times larger than a voltage applied to a normal pixel, thereby causing sudden liquid crystal displacement. The sudden liquid crystal displacement results from a rising time given by the following equation:Rising Time(τon)∝r1d2/ε0Δε(V2−Vth2)  (2)
In equation (2), when there is an affect of the pre-stage gate line GLn−1, Vth=1.0V and ΔV=10V.
The following equation represents a variation in rising time according to an affect of the pre-stage gate line GLn−1, when the charged voltage is 5V:Rising Time(τon)∝r1d2/ε0Δε(15.02−1.02)  (3)
As described above, owing to an affect of the pre-stage gate line GLn−1, the pixel voltage Vpixel becomes a sum of the charged voltage and the deriving voltage ΔV, which is equal to 15V. Since a liquid crystal response speed is inversely proportional to a square of the pixel voltage Vpixel, the rising time significantly increases. If the rising time increases too quickly due to an affect of the pre-stage gate line GLn−1, then liquid crystal displacement occurs. Since the rising time is inversely proportional to a square of an applied voltage, sudden liquid crystal displacement causes a brightness change for each frame to generate a flicker phenomenon, as shown in FIG. 8.
Alternatively, by locating the storage capacitor Cst at an area other than the pre-stage gate line GLn−1, an affect of the pre-stage gate line GLn−1 can be eliminated. For example, a storage-common-gate (SCG) structure in which the storage capacitor Cst is connected to a common electrode line SCL is shown in FIG. 9. However, a storage-capacitor-gate (SCG) structure is disadvantagous in that a pixel aperture ratio is reduced by 5% as compared to the storage-on-gate (SOG) structure. In addition, a total number of processes for forming the storage capacitor Cst increases.